Topic: - Study of various RISC and CISC processors
This term paper presents two instructions set architectures, particularly the CISC and the RISC, which have been developed as computer architects aimed for a fast, cost-effective design. Included in this paper are the arguments made for each architecture, and of some performance comparisons on RISC and CISC processors. These data
are collected from various papers published concerning the RISC versus CISC discussion.
RISC, or Reduced Instruction Set Computer is a type of microprocessor architecture that utilizes a small, highly-optimized set of instructions, rather than a more ...view middle of the document...
* pipelining: a technique that allows for simultaneous execution of parts, or stages, of instructions to more efficiently process instructions;
* large number of registers: the RISC design philosophy generally incorporates a larger number of registers to prevent in large amounts of interactions with memory
During the late 1980s and early 1990s, RISC processors began to replace CISC in the embedded applications which account for almost all microprocessor volume, and by the end of the decade market consolidation was well under way.
Types of RISC processors:- Alpha, ARC, ARM, MIPS, SPARC.
Some types are described below:
1. Alpha, originally known as Alpha AXP, is a 64-bit reduced instruction set computer (RISC) instruction set architecture (ISA) developed by Digital Equipment Corporation (DEC), designed to replace the 32-bit VAX complex instruction set computer (CISC) ISA and its implementations.
2. ARM is a 32-bit reduced instruction set computer (RISC) instruction set architecture (ISA) developed by ARM Holdings. It was named the Advanced RISC Machine, and before that, the Acorn RISC Machine. The ARM architecture is the most widely used 32-bit instruction set architecture in numbers produced. Originally conceived by Acorn Computers for use in its personal computers, the first ARM-based products were the Acorn Archimedes range introduced in 1987.
Characteristics of RISC processors:-
* Uniform instruction format, using a single word with the opcode in the same bit positions in every instruction, demanding less decoding;
* Identical general purpose registers, allowing any register to be used in any context, simplifying compiler design (although normally there are separate floating point registers);