Flip-Flops and Related Devices
1 . A "D" flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states? [Hint]
CLK = NGT, D = 0
CLK = PGT, D = 0
CLOCK NGT, D = 1
CLOCK PGT, D = 1
Both a and c
2 . Which statement BEST describes the operation of a negative-edge-triggered D flip-flop? [Hint]
The logic level at the D input is transferred to Q on NGT of CLK.
The Q output is ALWAYS identical to the CLK input if the D input is HIGH.
The Q output is ALWAYS identical to the D input when CLK = PGT.
The Q output is ALWAYS identical to the D input.
Only one of the inputs can be high at a time.
The output complement follows the input when enabled.
9 . Edge-triggered flip-flops must have: [Hint]
very fast response times.
at least two inputs to handle rising and falling edges.
a pulse transition detector.
active-low inputs and complemented outputs.
10 . What is the significance of the J and K terminals on the J-K flip-flop? [Hint]
There is no known significance in their designations.
The J represents "jump," which is how the Q output reacts whenever the clock goes high and the J input is also high.
The letters represent the initials of Johnson and King, the co-inventors of the J-K flip-flop.
All of the other letters of the alphabet are already in use.
11 . If both inputs of an S-C flip-flop are low, what will happen when the clock goes high? [Hint]
An invalid state will exist.
No change will occur in the output.
The output will toggle.
The output will reset.
12 . Which of the following best describes the action of pulse-triggered FF's? [Hint]
The clock and the S-C inputs must be pulse shaped.
The data is entered on the leading edge of the clock, and transferred out on the trailing edge of the clock.
A pulse on the clock transfers data from input to output.
The synchronous inputs must be pulsed.
13 . Which of the following is a disadvantage of the S-C master-slave flip-flop? [Hint]
The outputs do not change when both inputs are low.
There is no complementary output.
Data can only be entered on the leading edge of the clock.
An invalid output state exists if both inputs are high.
14 . Which of the following is not generally associated with flip-flops? [Hint]
Propagation delay time
15 . The waveforms shown in Figure 5-1 are applied to a gated D latch, which is initially RESET. Which of the areas identified on the Q waveform is incorrect?
16 . What is another name for a one-shot? [Hint]
17 . Given the waveforms for the S-C flip-flop in Figure 5-2, what is wrong with the circuit?
The Q output should be high at the beginning of the second clock pulse. The IC is defective.
When both C and S are high at the same time, the output is unpredictable. Nothing is wrong with the circuit.
The outputs should change on the trailing edge of the clock; the clock signal is inverted.
The outputs should have toggled on the leading edge of the second clock pulse; the IC is bad.
18 . A gated S-C latch and its associated waveforms are shown in Figure 5-3. What, if anything, is wrong and what could be causing the problem?
The output is always low; the circuit is defective.
The Q output should be the complement of the output; the S and R terminals are reversed....