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Exploiting Memory Access Patterns To Improve Memory Performance In Data Parallel Architectures

3745 words - 15 pages

Lecture critique et synthèse de: Exploiting Memory Access Patterns to Improve Memory Performance in Data-Parallel Architectures

Jean-François Patenaude

Département de génie logiciel et des technologies de l’information, École de technologie supérieure
1100 rue Notre-Dame Ouest, Montréal (Québec) H3C 1K3 Canada

Abstract—On retrouve une quasi-ubiquité de GPU permettant les calculs en tout genre (GPGPU) sur le marché. Or, il y a encore peu de logiciels qui en prennent avantage. Une de ces raisons est la complexité du développement de logiciels parallèles sur les GPU. C’est en grande partie parce que la gestion de la mémoire est laissée aux soins du développeur. D’ailleurs, une mauvaise ...view middle of the document...

En effet, il est maintenant très facile de se procurer une carte graphique qui permet de faire du GPGPU. En fait, depuis l’année 2006, la majorité des cartes graphiques vendues contiennent un processeur graphique qui supporte le GPGPU. C’est lors de cette année qu’AMD et NVIDIA, sortaient leurs outils de développement de GPGPU de pair avec leurs nouveaux GPU offrant plus de programmabilité [2], [3].
Or, les programmes parallèles ont un niveau de complexité plus élevé que les programmes séquentiels. En effet, les compilateurs n’étant pas encore assez évolués et matures, il en revient aux développeurs d’optimiser l’utilisation de la mémoire.
Quatre chercheurs, Byunghyun Jang, Dana Schaa, Perhaad Mistry et David Kaeli, se sont penchés sur l’étude des patrons d’accès de la mémoire afin d’y déceler des optimisations possibles [4]. Il s’agirait donc de définir une méthodologie qui garantirait de meilleures performances pour certains cas typiques. Deux différentes techniques sont alors présentées et testées selon l’architecture parallèle sous-jacente. Il y a donc la vectorisation obtenue par une transformation sur les données d’entrée pour les architectures vectorielles et la sélection algorithmique de l’espace mémoire pour les architectures scalaires.
Voyons si l’application de la méthodologie présentée par ces chercheurs tient la route et si elle parvient à faciliter la tâche des développeurs pour le développement de programmes parallèles.

Background
• Architecture scalaire : architecture qui n’est pas vectorielle dans le sens où elle ne fait qu’une opération à la fois, mais avec plusieurs threads. On parle du modèle d’exécution Single Instruction Multiple Threads (SIMT) et il est très utile pour paralléliser les programmes qui ne sont pas vectorisables.
• Architecture vectorielle : les opérations mémoire et les calculs sont effectués sur jusqu’à 4 éléments à la fois. La vectorisation des données permet alors de faire jusqu’à 4 fois plus d’opérations en même temps.
• Coalescence de la mémoire (Memory Coalescence) : fusion de blocs adjacents de mémoire afin de remplir l’espace libérée par de la mémoire désaffectée.
• CPU : Unité de traitement centrale (Central Processing Unit), là où est normalement exécuté le traitement séquentiel.
• Foulée non unitaire (non-unit stride) : un saut qui n’est pas unitaire, par exemple un saut de 3 ou de 2*indice.
• Fractionnellement vectorisable : lorsque seulement une partie des tableaux peut être mappée directement aux vecteurs.
• GPGPU : calcul générique sur un processeur graphique (General Purpose computing on Graphics Processing Units), consiste à utiliser le processeur de la carte graphique pour d’autres fins que les calculs graphiques.
• GPU : unité de traitement graphique (Graphic Processing Unit), le processeur graphique.
• Intrinsèquement vectorisable : lorsque tous les tableaux peuvent être directement mappés aux vecteurs sans nécessité de transformations.
• Loi d’Amdahl : selon cette loi,...

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